1. Technical Field
The present invention relates generally to memory in computer processing systems and, in particular, to a method for representing unvalues in the memory of a computer processing system, without requiring additional bits.
2. Background Description
Unvalues are no values. No legal computations can be performed with unvalues. Operations on unvalues typically either raise an exception or result again in unvalues. Unvalues are generally used for detecting the use of uninitialized variables. Moreover, unvalues may be used for propagating invalid computational results such as overflows, and for detecting illegal uses of such invalid results. Further, unvalues may be used for deferring exceptions, particularly when data is accessed speculatively, such as, for example, in the Multiflow Computer and in the Impact Epic architecture.
Conventional methods for representing unvalues in a computer processing system require special hardware in the computer processing system such as value bits or tag bits to differentiate between unvalues and valid values. Such conventional methods have thus increased the complexity and cost associated with implementing unvalues in computer processing systems.
Accordingly, it would be desirable and highly advantageous to have a method for implementing unvalues which is less complex and costly than the prior art methods for accomplishing the same.
The problems stated above, as well as other related problems of the prior art, are solved by the present invention, a method for representing unvalues in the memory of a computer processing system. The method of the invention represents such values without adding bits to the computer processing system.
In a first aspect of the invention, there is provided a method for representing unvalues in an unvalue-unaware memory of a computer processing system. The method includes the step of selecting arbitrary bit combinations to represent the unvalues, upon startup of the system. Upon performing a read operation from the memory, a read value is interpreted as an unvalue, when the read value matches at least one of the bit combinations. Upon performing a write operation to the memory, a value-unvalue-collision exception is raised, when a valid value is written to the memory and the valid value matches at least one of the bit combinations.
In a second aspect of the invention, the selecting step further includes the step of generating a plurality of unvalue encodings. The method further includes the step of, for either one of the read operation and the write operation, selecting one of the plurality of unvalue encodings as a current unvalue encoding.
In a third aspect of the invention, the step of selecting the current unvalue encoding for the read operation includes the step of extracting some bits from one of a virtual address and a physical address corresponding to the read operation. The current unvalue encoding is selected, based on the extracted bits.
In a fourth aspect of the invention, the step of selecting the current unvalue encoding for the write operation includes the step of extracting some bits from one of a virtual address and a physical address corresponding to the write operation. The current unvalue encoding is selected, based on the extracted bits.
In a fifth aspect of the invention, the plurality of unvalue encodings are one of pseudo-random numbers and random numbers.
In a sixth aspect of the invention, each of the plurality of unvalue encodings are word-wide, and the method further includes the step of classifying a word value as matching the current unvalue encoding, when the word value is equal to the current unvalue encoding, the word value being one of read and to be written.
In a seventh aspect of the invention, each of the plurality of unvalue encodings include less bits than a predetermined word-size of the memory. The method further includes the step of classifying a word value as matching the current unvalue encoding, when a Boolean function applied to the word value and the current unvalue encoding evaluates to true, the word value being one of read and to be written.
In an eighth aspect of the invention, the function evaluates to true for a single word value, when the function is applied to any of the plurality of unvalue encodings.
In a ninth aspect of the invention, the function evaluates to true for a plurality of word values, when the function is applied to any of the plurality of unvalue encodings.
In a tenth aspect of the invention, the method further includes the step of allowing a given TLB entry in a translation lookaside buffer (TLB) of the computer processing system to selectively enable or disable unvalue checking on a virtual page that is specified by the given TLB entry. A word value corresponding to one of the read operation and the write operation never matches any of the plurality of unvalue encodings when the given TLB entry disables the unvalue checking.
In an eleventh aspect of the invention, the method further includes the step of enabling at least one processor instruction to at least one of read and write the unvalues from and to the memory, respectively, without raising a corresponding exception.
In a twelfth aspect of the invention, the method further includes the step of enabling at least one processor instruction to raise an exception when the at least one processor instruction attempts to at least one of read and write a given unvalue from and to the memory, respectively.
In a thirteenth aspect of the invention, the method further includes the step of holding the current unvalue encoding in an unvalue register of a processor of the computer processing system.
In a fourteenth aspect of the invention, the method further includes the step of holding at least a subset of the plurality of unvalue encodings in unvalue registers included in a translation lookaside buffer (TLB) of the computer processing system. One of the plurality of unvalue registers is selected as a current unvalue register, based on a virtual address corresponding to one of the read operation and the write operation.
In a fifteenth aspect of the invention, the method further includes the step of holding at least a subset of the plurality of unvalue encodings in a plurality of unvalue registers included in a processor of the system. One of the plurality of unvalue registers is selected as a current unvalue register, based on a physical address corresponding to one of the read operation and the write operation.
In a sixteenth aspect of the invention, the method further includes the step of holding the current unvalue encoding in an unvalue register located in an interface between an unvalue-aware cache and an unvalue-unaware next-level memory. The cache has hardware means adapted to differentiate between the unvalues and valid values. The next-level memory has an absence of the hardware means.
In a seventh aspect of the invention, the method further includes the step of holding the plurality of unvalue encodings in a plurality of unvalue registers located in an interface between an unvalue-aware cache and an unvalue-unaware next-level memory. The cache has hardware means adapted to differentiate between the unvalues and valid values. The next-level memory has an absence of the hardware means. One of the plurality of unvalue registers is selected as the current unvalue register, based on a physical address corresponding to one of the read operation and the write operation.
In an eighteenth aspect of the invention, the method further includes the step of holding the plurality of unvalue encodings in a plurality of unvalue registers. The plurality of unvalue registers are supplemented with an unvalue-domain register. A current unvalue register is selected from the plurality of unvalue registers, based on at least one of a value stored in the unvalue-domain register and a portion of a physical address. The physical address corresponds to one of the read operation and the write operation.
In a nineteenth aspect of the invention, the plurality of unvalue registers and the unvalue-domain register are located in at least one of a processor and an interface of the system. The interface is disposed between an unvalue-aware cache and an unvalue-unaware next-level memory. The cache has hardware means adapted to differentiate between the unvalues and valid values. The next-level memory has an absence of the hardware means.
In a twentieth aspect of the invention, the method further includes the step of permitting the unvalue register to be selectively enabled and disabled. A value corresponding to one of the read operation and the write operation never matches the unvalue register when the unvalue register is disabled.
These and other aspects, features and advantages of the present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.